Introduction

The Arithmetic Logic Unit (ALU) is a vital hardware component of any digital computer. It is used to perform arithmetical and logical operations, such as addition, subtraction, incrementing, decrementing and bitwise-comparison. The ALU is typically contained within CPU chips, although it can be a dedicated piece of hardware, such as in the case where high speed number crunching is required. Microprocessors have one or more registers called accumulators or general registers, whereby data from these registers is loaded to and from the ALU when carrying out operations.



Half Adder

The basic module used in arithmetic elements is the half-adder. Its function is to add two binary digits or bits A and B, producing the sum S and carry C bits. Respectively the sum has an “Exclusive-Or” relationship, and the carry has an “And” relationship between its addend input A and augend input B. By itself the half-adder is not very useful as it can only add two bits of data.




\( \begin{align} S = (\overline A \wedge B) \vee (A \wedge \overline B) \\ C = A \wedge B \\ \end{align} \)



Full Adder

The full-adder can be can be constructed by combining two half-adders with an “Or” gate. Unlike the half-adder, the full-adder is able to handle carries from other binary digit stages. Constructing a full-adder from two half-adders is not the most efficient use of logic gates, but it does serve to illustrate the modularity of the half-adder. Notice we now have a carry-in bit, Ci.




\( \begin{align} S = (Ci \wedge \overline A \wedge \overline B) \vee (\overline Ci \wedge \overline A \wedge B) \vee (\overline Ci \wedge A \wedge \overline B) \vee (Ci \wedge A \wedge B) \\ Co = (Ci \wedge B) \vee (Ci \wedge A) \vee (A \wedge B) \\ \end{align} \)

Parallel Adder

This notion of modularity can be extended by combining multiple full-adders to form a parallel-adder. The figure shows a 4-bit parallel-adder capable of adding two 4-bit binary integers. The addend input lines labelled A0-A3 and the augend input lines labelled B0-B3, and with the addition result appearing on output lines S0-S3.

The parallel-adder is also capable of performing the subtraction. This is achieved by inverting the subtrahend input lines B0-B3 and setting the input Add/Sub bit high, which has the effect of taking the 2’s-complement of the subtrahend. When the subtrahend is added to the minuend input lines A0-A3, the subtraction result appears on the output lines S0-S3. If the output sign bit is high then the result is positive, if the sign bit is low, then the two’s complement of the output lines S0-S3 will be the result and it is negative.

There is no limit to the number of full-adders that can be cascaded. However there is an obvious delay in the circuit, as the carry propagates through each binary adder. This delay propagation is called the “carry-ripple problem”. A common technique to alleviate this problem can be achieved by using a “carry-look-ahead” circuit.




\( \begin{align} S = A + B \\ \end{align} \)

The TTL 74181 ALU

The SN74181 is a 4-bit binary Transistor-Transistor-Logic (TTL) integrated circuit in the 24-pin Dual-In-Line Package (DIP), originally manufactured by Texas Instruments in March 1970. This ALU chip was considered a breakthrough at the time and consequently used in mini computers of the time such as the DEC PDP-11, the DEC VAX 11/780 and the Xerox Alto. The 74181 provides multi-level carry look-ahead circuitry to minimise the carry-ripple problem. Without this circuitry, delay propagation issues would have been a problem especially as eight 74181 were cascaded in the case of the VAX11/780 32-bit machine.

The 74181 is able to perform a variety of arithmetical or logical operations depending on the logic state of input pin M (L = logical, H = arithmetic).




74181 Simulation and Reality

These 74181 chips are getting harder to find since they have not been manufactured since 1994, having been rendered obsolete by modern microprocessors and microcontrollers having their own internal ALU. However by looking hard enough it is still possible to find sources of new old stock samples for experimentation purposes.




The photo shows a 74181 wired up to a breadboard with some LEDs and DIP switches. Observe that the DIP switches positions have put the 74181 into arithmetic mode (M = L, S0 = H, S1 = L, S2 = L, S3 = H). Since the 74181 expects the 4-bit input words to be inverted, setting Cn = H compensates for this. The binary digit of 2 is being applied to addend input lines A0-A3, and the binary digit of 10 is being applied to the augend input lines B0-B3, which results in an output result of 12 (F0 = L, F1 = L, F2 = H, F3 = H). Showing that two plus ten does in fact equal twelve.

If it is not possible to source a 74181 for experimentation purposes, all is not lost as there is an excellent digital logic designer aptly name Digital which is able to simulate digital circuits such as the breadboard circuit above, as well as having many other features. The figure below shows the simulation when using Digital. Notice the simulation agrees with breadboard reality, which always is encouraging.




External References

74181
Digital