As already mentioned the circuit is a standard design. The PLL, when operating within its operating range, will
acquire and lock to the input signal, track it in frequency, and exhibit a fixed phase relationship relative to the
input. The MC4044 chip contains two phase detectors, a charge pump and an amplifier. Detector #1 is a phase and
frequency detector whose output is connected to the charge pump. This serves two purposes; to generate an error
voltage proportional to the phase or frequency difference and in conjunction with the amplifier to serve as the loop
filter. Detector #2 a simple exclusive-or phase detector which is able to acquire a quadrature lock and is used to
indicate an out of lock (slip indicator) condition.
The loop filter components are chosen to set the loop bandwidth, capture time and transient response, and are
primarily characterized by R1, R2 and C1. Q1 is connected as an emitter follower and is used to buffer the
amplifier, this allows for R1 to be increased when a lower phase detector gain stage is required. The error signal
from the amplifier output is fed into the OSC5A2B02 OCXO Vref pin to trim the 10MHz square wave output frequency. This
output square wave is fed into the 74HC4017 decade counter which divides the 10MHz output frequency down for
comparison by the phase detector, thus closing the control loop.